Bought a fancy Tigard JTAG adapter instead of the USB Blaster clone I’ve been using.
Need to figure out how to bump performance further, but even at default low speeds in urjtag, it seems like a good improvement.
When I converted this Mushi to Pink Sweets Suicide Club, I fucked up a bit and used bad blocks on U2, which is causing minor sprite glitches now. Going to see if I can fix it easily with JTAG so I don’t have to swap the IC again.
Disclaimer: This is mostly written for myself. It will be hard to follow. Maybe someone will find it interesting anyways.
Following up on the earlier posts on CV1000 research, I’ve been looking at making a patch for MAME implementing this, but got a nice report from a tester that the current implementation I did had weird amounts of delay after the second midboss in Pink Sweets. This was mostly due to a silly mistake in my code, which was good to find, but when looking at the actual delays from a PCB running Pink Sweets, I still seemed to be off by quite a bit.
This caused me to spend another week or so figuring out what was up, and I first made some sortof interesting observations regarding clipping:
Additionally, I realized that the simplified calculations described in my PDF writeup was faulty. While the general thinking and memory layout was described correctly, write alignments may cause also cause additional delays. This will be described further below as well.
Pink Sweets uses and interesting drawing method in sections with scrolling backgrounds featuring “wavy patterns”, where it sets up parts of the background in a separate area in VRAM before copying it to the visible buffer. These copies are done as many 1×324 pixel draws, with offsets varying by up to 4 pixels to generate the waves.
These draws will also be performed outside of the visible clipping area, and by instrumenting MAME I could see these type of fully invisible draws happening 80 times per frame in a single sequence.
This will look pretty interesting in a logic analyzer attached to a PCB. In the image below, the “BACK” pulses on the bottom row is the Blitter reading operations from SRAM. Each pulse will read 64 bytes of data, which means that a total of 1600 bytes are read. Since each Draw operation is 20 bytes, this maps exactly to the 80 “invisible” Operations.
This means two things in terms of delay simulation:
The way the waves in the Pink Sweets background is generated is by modifying the start offset in a curve with amplitude 4. Most of these draws will start slightly below the visible area.
As an example, a draw may be (note that X/Y are rotated, due to TATE):
// CLIP_AREA is MIN_X=416, MAX_X=735, MIN_Y=128, MAX_Y=368 SRC_X=864, SRC_Y=128 DST_X=414, DST_Y=128 SIZE_X = 324 SIZE_Y = 1
This means that the write to (X=414,Y=128) and (X=415,Y=128) will not be in the visible area. Looking at a logic analyzer output of this write, it is however still written. The image below has some glitches in the signals, but is annotated for clarity.
1: Read 32 pixels of source data, nicely aligned in same VRAM row.
2: Read 2 pixels of destination for the VRAM row of the invisible data.
3: Write the 2 invisible pixels to that VRAM row.
4: Read remaining 30 pixels of destination data
5: Write the 30 pixels of destination data.
(In practice, this will actually read 4 and 32 pixels instead, since all operations work at 4 pixels per VRAM CLK, but that doesnt matter much).
Since each additional VRAM row access has significant overhead, this means that there’s some wasted work going on here… and it gets worse!
In my large writeup earlier, I had the following calculation for Draw operations.
VRAM_ROW_HEIGHT = CEIL( ( (IMAGE_Y % 32) + IMAGE_HEIGHT ) / 32 )
VRAM_ROW_WIDTH = CEIL( ( (IMAGE_X % 32) + IMAGE_WIDTH ) / 32 )
NUM_VRAM_ROWS = VRAM_ROW_HEIGHT * VRAM_ROW_WIDTH
NUM_VRAM_CLK = (NUM_PIXELS * 3 / 4) + NUM_VRAM_ROWS * (5 + 20 + 10) + 10
Time Needed = NUM_VRAM_CLK * 13ns
This has two major issues. First it assumes that the number of pixels being read from source data, and the number of pixels read+written to destination are equal. As described in the section “Writes are always done four pixels at the time, to offsets evenly divisible by four“, this is not true. There can be four pixels of overhead per line, depending on alignment.
Secondly, this assumes that each VRAM row written to, will only be written to once. Depending on alignment, this may also be false. If drawing a sprite with X_SIZE=64, Y_SIZE=1 to position X=16,Y=0, the following sequence will happen:
Every read+write to a destination VRAM row will add 35 CLK of overhead, so even if the number of rows written to here are just 3, the total access overhead will be for 4 VRAM row accesses. The actual calculation should be something like:
NUM_VRAM_CLK = (SRC_PIXELS / 4 + DST_PIXELS * 2 / 4)
+ NUM_DESTINATION_VRAM_ACCESSES * (5 + 20 + 10) + 10
Time Needed = NUM_VRAM_CLK * 13ns
Calculating the number of VRAM accesses can be done iteratively, but there’s probably a nice formula for it as well, that I’m too tired to figure out right now.
Finally to show how big the difference can be in Draw latency depending on how the destination is aligned in VRAM rows, both of the picture above show the first 32 bytes of data being written for a 324×1 pixel part of the background. Image one is aligned will with destination VRAM rows, while the second image is off by 2 pixels.
As an extra footnote to the CPU Slowdown post about Akai Katana, here’s two more fun pictures, showing other stuff that can happens.
First, there are actually some rare occasions where Blitter induced slowdown can matter. This happens very rarely in Akai Katana, but sometimes when there’s a lot of draws going on, the Blitter processing takes more than a frame, and we can see the CPU repeatedly doing ready checks by pulsing CS6.
As mentioned earlier, this is very infrequent in this game, and almost all slowdown is just CPU being slow.
The other fun thing is that the CPU often does enough work that it doesn’t even have time to process it in two frames, which means several frames of slowdown. The example below shows CPU processing and waits causing two extra frames of slowdown, but more can happen too.
It really feels like this was rushed out without much thought given to performance.
When looking at CV1000 Blitter performance, one thing I noticed was that behavior seemed to differ heavily between games, and on some games, despite not seeing long Blitter operation lists, there is heavy slowdown.
The main offender here is Akai Katana, which will have very heavy slowdown when in Spirit mode, reflecting bullets. For some PCB footage, here’s an old video I made.
This slowdown comes despite not a lot of draws happening, which indicates that it’s related to CPU. I went ahead and verified this.
When there’s no slowdown and game runs on full speed, we can see the following behavior.
For captures below, the signals from top to bottom are:
First here’s a non-slowdown section.
When a VSYNC pulse triggers, Blitter operations kick off. These finish well ahead of the next VSYNC. When looking at CS3 pulses, we can see that these become much less frequent a while before VSYNC. This is when the CPU has finished executing game logic and is waiting for the next frame. Since logic finished before a new pulse, things are fine here.
Now lets look at that chunky Akai Katana slowdown.
The main difference here is that the CPU is actively doing work longer than a single frame, as can be seen by looking at CS3 working past the next IRQ2 pulse. This means that the CPU will ignore the interrupt, and then start spin-waiting for a new one. This causes one frame of slowdown.
For some games like Akai Katana, getting the Blitter timing accurate is not going to do anything for accuracy in emulation.
What is instead needed is work on the SH-3 emulation.
Current MAME emulation of the CPU does not support the wait states introduced by RAM accesses that either are uncached, or results in cache misses. The actual cache behavior is described in-depth in the SH-3 datasheet an should be rather simple to implement, but getting the wait-state handling in place seems pretty hard (especially with dynamic recompilation enabled).
There’s also wait states for stuff like U2, Audio, EEPROM, … accesses, but compared to RAM this doesn’t seem to be a big deal.
For some other CV1000 games, the Blitter timing does matter though, so getting both parts right is needed to get something that is truly behaving similar to the actual boards.
I’ve spent some time in December looking into CV1000 Blitter behavior to figure out how it performs in terms of slowdown. I feel I have a good understanding of how it works now, and have put together a doc describing it.
View/Download it here: CV1000_Blitter_Research_by_buffi.pdf
The current simulation of this Blitter in MAME is quite impressive as a high-level reproduction, but there doesn’t seem to have been much time spent researching the timing of operations.
This document aims to document how the behavior and timing of the Blitter actually works, and people can utilize this to make something that’s mostly accurate.
Also it is very fun to attach a Logic Analyzer to a PCB and figuring out how it works.
Q: But what about tuning Blitter Delay in MAME
A: Trying to tune the existing Blitter Delay slider in MAME doesn’t really make any sense, since the slowdown introduced from it doesn’t have anything to do with how it works on real hardware. It’s still arguably better than no slowdown at all, which used to be the other option, but that’s about it.
Q: Will this make CV1000 emulation run with proper slowdown?
A: Probably not really. While this should make it possible to have the Blitter part of emulation more accurate, there’s still no emulation of SH-3 Wait States either, which means that slowdown that’s due to CPU not having time to finish processing before VBLANK due to waiting will still not be accurate. I have no idea how much this matters for most games.’
Q: How much work is it to implement this?
A: It should be very simple. And the simplest thing to do would be:
This still doesn’t reflect how it’s performs on real hardware (where Operations are running concurrently with the CPU, and requesting new Operations when the existing ones are done executing), but in practice I don’t think that should really matter in terms of experienced gameplay performance.
If you have feedback on the document, or suggestions for further work, please reach out to me on Arcade-Project forums, Github or in comments on this blog.
Some Cave game difficulty rankings have been going around the Twitterverse recently, so thought I’d post my opinions and list, with some motivations behind the entries.
This is how I’d rank the difficulty of most Cave games in one credit. Videos of me clearing them are attached for all titles.
Picked up a Batsugun PCB, as partial trade for my Ibara Kuro. Looking forward to trying this out. My cab is currently in horizontal mode, so will have to rotate it first though. Might play some more horisontal games for now first.
One of my goals for this year is to sell games for more money then I spend, which means getting rid of some of the pricier items I own. This includes my Ibara Kuro PCB that I bought last year. This has gotten so expensive now that it’s hard to motivate keeping it, and I’ve finally sold it and shipped it away to its new owner today.
Ibara Black Label (also known as Ibara Kuro) is a remake of Ibara that plays nothing like the original game. Instead of playing like a typical Yagawa shmup, you have a dynamic rank system which increases with medal pickups, and resets on bombs and big cancels. In addition, there’s a multiplier that increments when grazing enemy bullets, which is not a system you’d typically see in Cave games.
Since the PCB is very rare and there’s so far no ports of this game on any non-arcade platform, the price of a PCB has shot up by a lot. While it’s a cool and unique game, I don’t think I’ll play it too much more (I prefer regular Ibara), and I’d rather spend that money elsewhere.
For character selection, I like Bond Type D for his speed and bomb. I’m not sure how much of a difference it makes in practice.
Stage 1: My execution of the initial scoring is pretty flawed, but start by setting up a Hadou Gun, and build a medal chain to increase your rank. Then later on, move to the top left corner and graze the big stream of bullets, to build a big counter for a cancel, to get some points towards an extend. There’s another nice stream of bullets you can setup later on as well (watch the video). No specific strats for the boss. Don’t be afraid to bomb. No missing this stage shouldn’t be a huge problem
Stage 2: I tend to use 5 Way for most sections with small enemies, and rockets for the larger ones. I don’t do any impressive scoring at all on this stage, but just focus on keeping the medal chain alive. The trickiest section to route is the part before the two flame towers. I recommend just replicating the video for that.
On the boss, start by staying above the first phase and taking it out that way, similar to regular Ibara. For phase two, follow a Hadou Gun up the right side of the screen to build rank from medals, and then park yourself in the safe spot right below the health bar. This will allow milking a lot of points towards an extend.
Stage 3: Rockets feel quite strong here. Try to keep medal chain going and start getting a lot of bombs. I’ll use a hadou gun or two towards the later trains, but like to reach the boss with full bomb meter. For the boss, I’ll hadou it once when it gets to unmanageable, and that should be enough.
Stage 4: For the extend ship, I start by damaging it’s right side with a hadou gun activation that I fire on the left side. Then I can sit and safe spot it above the right bullets while building multiplier for some free points towards extend. 5 Way is very strong in this stage, and should basically be used at all times until the big end ships which Napalm work better against. Try to be at max bombs for the boss.
The boss itself is pretty easy in phase 1, but will likely require a hadou gun for it’s second phase which has very dense patterns.
Stage 5: For the first section, small movements with rockets are kep. You can use the same trick with double hadou guns to get full bomb pickups from the tanks as in big Ibara. Just place them in a way so that they’ll destroy both sides of the tanks tracks, without hitting the tanks themselves. 5 Way is very strong at the later parts of the stage since there’s so many small enemies.
For the boss, I quick kill phase 1 by placing a hadou gun shot at the edge of it’s sprites. It then has some pretty silly safe spots for phase 2, which trivializes that part of the fight (see video). You can milk this quite a bit if you want. The last phase is total bullshit and will need two hadou gun shots.
Stage 6: 5 Way is once again very strong. I trigger a pretty late third extend here in my video. Ideally I’d have it earlier, but three extends is what I’d typically end up with on my route.
For the boss, I just rely on my hadou gun shots for anything that looks scary. In my clear, I get really really awkward hadou gun shots, since hitting the enemies that the boss spawns will do very little damage. This causes me to have to do some pretty silly dodges. If you can instead tag the boss in its last phase with two of them, it should be enough.
Pink Sweets is easily one of Caves hardest games, but on PCB there’s an infinite lives glitch that can be triggered, which trivializes the rest of the game.
This requires getting 4 extends without dieing, which is not much easier than a typical Cave 1CC. I got this a while ago, but finally took the time to record a quick commentary on how to trigger the glitch, if others are curious.
Extends spawn when you destroy 2500 enemies or destructible bullets, and then kill an enemy. This means you want to try to destroy as many destructible bullets as possible, especially on midbosses and bosses. This requires pretty careful planning.
On a good Stage 1 run, you should be able to get the zan counter to about 2000, triggering the first extend early on stage 2. If you trigger the first extend later in Stage 2, that’s not a huge problem since you can make up some on the Stage 2 boss, where I don’t care much about going for zan in this run.
S3 midboss is the make or break section of the run, since it’s very easy to mess it up, and it will sometimes give you random movements which makes it hard to trigger the deaths of side capsules when you want it.
For MAME practice, you can use the following lua script, to display the zan counter when playing, which simplifies routing. This will obviously not be helpful when playing for real on a PCB later as in the video above.
// Put this in pinkswts.lua
cpu = manager:machine().devices[":maincpu"]
mem = cpu.spaces["program"]
s = manager:machine().screens[":screen"]
function draw_hud()
cnt = string.format("CNT : %d", mem:read_i16(0x0c4a3ab6));
s:draw_text(225, 3, cnt);
end
emu.register_frame_done(draw_hud, "frame")
// And run game with mame64.exe pinkswts -autoboot_script pinkswts.lua
For completitions sake, here is my full 1CC using the glitch, but the rest of the run isn’t very exciting.
The game itself is pretty interesting. It plays sortof like Yagawa’s earlier games, but is much less forgiving, and rank control isn’t as doable since you no longer get point extends.
Going for a non-infinite lives 1CC is very hard, and seems easiest by completely skipping item pickups and playing very carefully. It seems unlikely that I’ll get back to doing that, since this isn’t really one of my favorite games.
Other than playing arcade games, I also enjoy messing around with the hardware, and I’ve finished up a few small CV1000 related projects recently.
I reverse engineered the behavior of the U13 CPLD, and wrote a compatible bitstream, that can be programmed to EPM7032 CPLDs. This allows repairing boards where the internal flash has gone bad. An indepth description of this is available at the project page: https://github.com/buffis/cv1k_research/tree/main/U13_Research
Ideally, it would be better to use the original bitstream of the CPLD, but it’s read protected, and no public dumps are available, so this is the second best thing.
I figured out how to use the JTAG port of the PCB’s to easily read/write the prog rom (U4) as well as the EEPROM. U2 reads/writes are also possible, but not recommended since they require some pretty sketchy bitbanging.
This allows for very simple dumping of U4, as well as upgrading to bugfix releases.
I’m fairly certain that more than a few other people have also figured this out earlier, but the information was not public until now. More info is available at the project page: https://github.com/buffis/cv1k_research/tree/main/JTAG